The present invention relates to a method and/or architecture for implementing sense amplifiers generally and, more particularly, to a method and/or architecture for implementing a current steering, reduced bitline voltage swing sense amplifier.
Referring to FIG. 1, a diagram of a memory cell 10 is shown. The memory cell 10 includes a transistor 12 and a transistor 14. The transistors 12 and 14 are implemented in silicon, oxide, nitride, oxide, silicon (SONOS) technology. Under nominal conditions, the transistor 12 is implemented as an enhancement mode (e.g., positive) threshold voltage transistor and the transistor 14 is implemented as a depletion mode (e.g., negative) threshold voltage transistor. However, under extended operating conditions, the threshold voltage of the enhancement mode device (i.e., the transistor 12) can become slightly negative (e.g., the transistor 12 can operate as a depletion mode device). The transistors 12 and 14 have a drain connected to a bitline (BL) or bitline bar (BLb), a gate connected in common to a wordline (WL), and a source that receives a read reference voltage (VR). The signals BL and BLb are passed through a selection device such that only one of many such bitline BL/bitline bar BLb signal pairs is coupled to a particular sense amplifier at a time.
A conventional read operation of the memory cell 10 includes the steps of: (i) isolating the sense nodes of the sense amplifier from a supply voltage (VPWR) and a ground potential (VGND); (ii) equalizing the sense nodes, (iii) applying a differential voltage of sufficient magnitude (about 100 mV) across the data nodes by addressing the memory cell 10, and (iv) simultaneously and gradually coupling the sense amplifier to the supply voltage VPWR and the ground potential VGND. As the sense amplifier powers up, the differential voltage between the data nodes is increased until the differential voltage is approximately equal to the supply voltage VPWR. The conventional method of implementing and operating the sense amplifier circuitry has the disadvantages of (i) not sensing very small signal currents and (ii) requiring high memory cell voltage swing.
Due to SONOS device behavior, the absolute voltage levels on the bitlines BL and bitline bars BLb must be limited. The conventional technique used in EEPROM, FLASH, DRAM, and SRAM depends upon application of a small data signal to the sense amplifier prior to enabling. The conventional technique can not be used with some implementations of SONOS memory transistors because of bias restrictions (i.e., SONOS implementations where the maximum voltage level at the bitline BL and the bitline bar BLb must be less than the supply voltage VPWR).
It is desirable to have method and/or architecture for a sense amplifier that may sense small signal currents while limiting memory cell voltage swing for any memory cell implementation.
The present invention concerns a method for reading a memory cell comprising the steps of (A) raising a voltage level of a bitline of the memory cell above a predetermined level, (B) detecting a current flow generated on the bitline in response to the raised voltage level, and (C) coupling one or more sense nodes coupled to the bitline to a ground potential when the current flow is above a predetermined magnitude.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a current steering, reduced bitline voltage swing sense amplifier that may (i) precharge bitlines to a voltage level where the memory cell is non-conductive, (ii) generate a desired voltage signal, (iii) use current steering to generate the desired voltage signal, (iv) use transistors to initiate signal generation by pulsing sense nodes and bitlines to a voltage level where the memory cell conducts current, (v) change the bias point of a sense amplifier, (vi) be used with floating gate non-volatile memory cells (e.g., FLASH, EEPROM, etc.), (vii) be used with a single transistor non-volatile memory cell, (viii) allow sensing of very small signal currents while limiting the voltage swing experienced by the memory cell, (ix) form the memory cell data signal, (x) use cross coupled P-channel transistors in a current steering mode to form the signal voltage, and/or (xi) be used with any memory cell implementation.